1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a metal oxide semiconductor field effect transistor (MOSFET) and a method of fabricating the same.
2. Description of the Related Art
A challenge of very large scale integration (VLSI) over the last few decades has been the constantly increasing integration of MOSFETs that have high yield and high reliability. This challenge has been met primarily by scaling down the channel length of the MOSFET while avoiding excessive short channel effects. As known in the art, the short channel effect refers to the reduction of a threshold voltage in a short-channel device due to a two-dimensional electrostatic charge shared by a gate region and source/drain regions.
It has been considered that a device that utilizes single crystal silicon should be made smaller to improve the integration, but limitations are caused by the short channel effect and an expected increase in the channel resistance. Nevertheless, because silicon has many advantages, much research has focused on overcoming the limitation of a silicon-based transistor. Silicon nanowires are a newly emerging technology which may prove to be an important key in overcoming the present limitations in the silicon-based industries. According to many simulations and computations, a nanowire MOSFET offers a very high electrical conductivity due to its structural characteristics, without the need for doping and without increased channel area resistance.
However, it is very complicated to fabricate a MOSFET having a fine nanowire structure.